Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Silicon Labs/Series0/EZR32HG/EZR32HG320F64R67/DMA/CHENC#0x0
Channel Enable Clear Register
Channel 0 Enable Clear
Channel 1 Enable Clear
Channel 2 Enable Clear
Channel 3 Enable Clear
Channel 4 Enable Clear
Channel 5 Enable Clear
https://github.com/cmsis-svd/cmsis-svd-data